Result Details

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. COMPUTING AND INFORMATICS, 2010, vol. 29, no. 6, p. 1359-1371. ISSN: 1335-9150.
Type
journal article
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D., DCSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Abstract

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.

Keywords

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

Published
2010
Pages
1359–1371
Journal
COMPUTING AND INFORMATICS, vol. 29, no. 6, ISSN 1335-9150
BibTeX 
@article{BUT50732,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units",
  journal="COMPUTING AND INFORMATICS",
  year="2010",
  volume="29",
  number="6",
  pages="1359--1371",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/9421/"
}
Files
Projects
Design and hardware implementation of a patent-invention machine, GACR, Standardní projekty, GA102/07/0850, start: 2007-01-01, end: 2009-12-31, completed
Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems, GACR, Doktorské granty, GD102/09/H042, start: 2009-01-30, end: 2012-12-31, completed
Secured, reliable and adaptive computer systems, BUT, Vnitřní projekty VUT, FIT-S-10-1, start: 2010-03-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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