Result Details
RTL benchmark circuit generator
Created: 2007
Type
software
Language
English
Authors
Pečenka Tomáš, Ing., Ph.D., FIT (FIT), DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Description
Cirgen is RTL (Register Transfer level) benchmark circuit generator. It utilizes the evolutionary algorithm to design a structure of a benchmark circuit automatically according to the testability requirements specified by the user. Cirgen can be downloaded from http://www.fit.vutbr.cz/~pecenka/cirgen/
Keywords
digital circuits, benchmark circuits, design tool, evolutionary algorithm, testability
Location
Software je společně se sadou vytvořených testovacích obvodů ke stažení z URL: http://www.fit.vutbr.cz/~pecenka/cirgen/
License
In order to use the result by another entity, it is always necessary to acquire a license
License Fee
The licensor does not require a license fee for the result
Projects
Design and hardware implementation of a patent-invention machine, GACR, Standardní projekty, GA102/07/0850, start: 2007-01-01, end: 2009-12-31, completed
Integrated approach to education of PhD students in the area of parallel and distributed systems, GACR, Doktorské granty, GD102/05/H050, start: 2005-01-01, end: 2008-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Integrated approach to education of PhD students in the area of parallel and distributed systems, GACR, Doktorské granty, GD102/05/H050, start: 2005-01-01, end: 2008-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments