Result Details

Low Power Testing

KOTÁSEK, Z.; ŠKARVADA, J. Low Power Testing. In Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012. p. 395-412. ISBN: 978-1-60960-212-3.
Type
chapter in a book
Language
English
Authors
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Škarvada Jaroslav, Ing., Ph.D.
Abstract

Portable computer systems and embedded systems are examples of electronic devices which are powered from batteries, therefore they are designed with the goal of low power consumption. Low power consumption becomes important not only during normal operational mode but during test application as well when switching activity is higher than in normal mode. In this chapter, a survey of basic concepts and methodologies from the area of low power testing is provided. First, it is explained how power consumption is related to switching activities during test application. Then, the concepts of static and dynamic power consumption are discussed together with metrics which can be possibly used to evaluate power consumption.  The survey of methods the goal of which is to reduce dynamic power consumption during test application is then provided followed by a short survey of power-constrained test scheduling methods.

Keywords

power consumption, low power testing

Published
2012
Pages
395–412
Book
Design and Test Technology foír Dependable Systems-on-Chip
ISBN
978-1-60960-212-3
Publisher
IGI Global
Place
Hershey
BibTeX
@inbook{BUT98565,
  author="Zdeněk {Kotásek} and Jaroslav {Škarvada}",
  title="Low Power Testing",
  booktitle="Design and Test Technology foír Dependable Systems-on-Chip",
  year="2012",
  publisher="IGI Global",
  address="Hershey",
  pages="395--412",
  isbn="978-1-60960-212-3"
}
Projects
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Departments
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