IVH Acad. year 2022/2023 Summer semester 4 credits
Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Language of instruction
- 26 hrs exercises
- 13 hrs projects
- 100 pts projects
Vašíček Zdeněk, doc. Ing., Ph.D. (UPSY)
Subject specific learning outcomes and competences
The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioural and structural description. This course is recommended as a co-requisite for INC and INP.
To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
Why is the course taught
The VHDL Seminar supports INC and INP courses and is recommended to deepen the knowledge of VHDL language and issues connected with advanced hardware design. Students will receive a more detailed knowledge of VHDL not only theoretically but also practically as there are not only practical demonstrations but also a project on FITkit, development board equipped with programmable gate array XILINX. Mastering the hardware description language is a key element in the successful and efficient design of FPGA-based systems having a dominant position especially in the field of high-performance computing (network operations acceleration, acceleration of digital signal and video processing, acceleration of bioinformatic tasks, cryptographic applications, etc.), where the acceleration platforms based on FPGAs can achieve significant speedup gain at minimum power levels compared to the conventional parallelization techniques based on CPUs and GPUs. Knowledge of hardware description techniques enables students to actively engage in a number of research projects in the area of network data and security processing.
Prerequisite knowledge and skills
Basic skills in programming and digital design, fundamentals of Boolean algebra.
- Jasinski, R.: Effective Coding with VHDL: Principles and Best Practice. The MIT Press. 2016.
- Pedroni, V. A.: Circuit Design and Simulation with VHDL (Second Edition). The MIT Press. 2011
- Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
- Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
- Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993
Syllabus of numerical exercises
- Modern hardware design (design flow), hardware description languages (VHDL, Verilog), FPGA, introduction to digital systems.
- Basic VHDL language structure, lexical description, VHDL source code.
- Data types, data objects, object classes, data object declaration.
- VHDL language statements
- Advanced VHDL language properties, time delay and scheduling.
- Combination circuits description, three-state circuits.
- Synchronous sequential circuits description, finite state automata description, asynchronous sequential circuits.
- Circuits modeling and event based simulation, circuit testing, test design, functional simulation (ModelSIM), co-simulation.
- Circuit synthesis, constraints, synthesis for FPGA, time simulation.
- Advanced methods (pipelining, retiming, component sharing, flattening and structuring)
- Complex circuit case study: LED matrix display, UART, ETHERNET
- Complex circuit case study: RISC processor
- FPGA circuits, mass parallelism in cryptography (RC4, DES), DNA-alignment
Syllabus - others, projects and individual work of students
Individual project dividend into several parts.
Project supported by the written technical report in the English language. Exam prerequisites: Class credit is gained when a minimum total score of 50% points is gained during a semester.
Class credit is gained when a minimum total score of 50 points is gained during a semester.
|Mon||exercise||1., 2., 3., 4., 5., 6., 7., 8., 9., 11., 12. of lectures||D0206||09:00||10:50||9999||1BIA 1BIB 2BIA 2BIB 3BIT||xx||Mrázek|
Course inclusion in study plans
- Programme BIT, 1st year of study, Compulsory-Elective group T
- Programme BIT (in English), 2nd year of study, Compulsory-Elective group T
- Programme IT-BC-3, field BIT, 1st year of study, Compulsory-Elective group T