Course details

# Digital Systems Design (in English)

INCe Acad. year 2023/2024 Winter semester 5 credits

Binary number system: positional notation, base conversion, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, the design of combinatorial logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Simple asynchronous networks: design and analysis of behaviour. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronous sequential networks: state coding, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital system: design CAD tools, description tools, design strategy. Integrated circuits families. Programmable logic devices.

Guarantor

Course coordinator

Language of instruction

English

Completion

Examination (written)

Time span

• 39 hrs lectures
• 13 hrs exercises

Assessment points

• 55 pts final exam (written part)
• 25 pts mid-term test (written part)
• 20 pts written tests (written part)

Department

Lecturer

Instructor

Learning objectives

The goal is to obtain fundamental knowledge in the design and analysis of digital circuits. To learn basic combinational and sequential logic circuits to design digital systems.

Practical use of selected methods for describing combinational and sequential logic networks. Mastering the analysis and design of simple combinational and sequential logic networks. Mastery of the analysis and design of simple digital devices constructed from combinational and sequential circuits and blocks.

Why is the course taught

The architectures of current processors and other computing systems are based on the basic principles of digital system design. With the development of digitalization, machine learning, and autonomous systems, the need for real-time processing of large data volumes increases significantly. There is a need to speed up computing systems to build them more efficiently with less power consumption. Without knowledge of digital circuit design, it is impossible to construct hardware accelerators or write efficient programs that use these accelerators. Therefore, the course aims to introduce students to the principles of digital design and take the first step towards knowing how to design hardware accelerators, understand them and use them effectively.

Recommended prerequisites

Prerequisite knowledge and skills

The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and essential active and passive electronic components.

Study literature

• Frištacký, N., Kolesár, M., Kolenička, J., Hlavatý, J.: Logické systémy. SNTL Praha, ALFA Bratislava, 1986.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
• Eysselt, M.: Vybrané příklady podporující návrh číslicových systémů. Studijní opora, Učební text, FIT, 2002, 38 str. Tento text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
• Eysselt, M.: Digital Systems Design: Programmable Logic Devices. Studijní opora, Učební text, FIT VUT v Brně, 2003. Zde je WWW verze přístupná evidovaným studentům.
• Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

Fundamental literature

• McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
• Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
• Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

Syllabus of lectures

1. Binary number system: positional notation, conversion of the base, binary codes, binary arithmetic.
2. Boolean algebra, logic functions and their representations, logic expressions.
3. Reduction methods: Karnaugh maps, Quine-McCluskey tabular method, Petrick's cover function.
4. Logic and functional diagrams. Analysis of logic networks behaviour: signal races, hazards.
5. Combinational logic: multiplexer, demultiplexer, decoder, coder.
6. Combinational logic: comparator, adder, subtractor, arithmetic and logic unit.
7. State machines and their representations.
8. Synchronized sequential networks: state coding, optimization and implementation.
9. Sequential logic: Registers, counters, shift registers.
10. VHDL language, logic circuits synthesis.
11. Design of simple digital circuits: CAD tools and design methodology.
12. Programmable logic devices.
13. Digital design patterns and optimisations.

Syllabus of numerical exercises

• Binary numbers: positional notation of numbers, conversions between systems, representation of binary numbers, binary arithmetic operations, codes.
• Boolean algebra, representations of logic functions.
• Quine-McCluskey tabular reduction method, Petrick's cover function.
• Reduction methods: Karnaugh maps, logic and functional diagrams.
• Implementation of logic functions.
• Selected logic modules: multiplexer, demultiplexer, encoder, decoder, adder, ALU.
• State machines. Design of synchronous digital circuits.
• Pprogrammable logic devices.

Progress assessment

The interim test: 20 points. Mid-term exam: 25 points. Final Exam: 55 points.
The passing boundary for ECTS assessment: 50 points.

Interim test, mid-term and final exams are monitored, points can be earned. The tests and mid-term examinations don't have an alternative date. The final exam has two alternative dates.

Exam prerequisites

Requirements for class accreditation are not defined.

Schedule

DayTypeWeeksRoomStartEndCapacityLect.grpGroupsInfo
Mon exam 2023-10-09 L304 14:0015:00 INCe - písemný test
Mon exam 2023-11-06 L304 14:0015:30 INCe - Půlsemestrální zkouška
Mon exam 2023-12-11 L304 14:0015:50 INCe - předtermín zkoušky
Mon exam 2023-12-18 L304 14:0015:50 INCe - 2. předtermín zkoušky
Mon lecture 2., 3., 4., 5., 6., 7., 9., 10., 11., 12., 13. of lectures L304 14:0016:5015 INTE xx Hussain
Mon lecture 2023-09-18 L304 14:0016:5015 INTE xx Kořenek
Mon exercise 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13. of lectures L304 17:0017:5015 INTE xx Hussain
Wed exam 2024-01-10 L304 09:0010:50 3. termín zkoušky
Fri exam 2024-01-05 L304 09:0010:50 2. termín zkoušky