Thesis Details

Aproximace obvodů v nástroji Yosys

Bachelor's Thesis Student: Plevač Lukáš Academic Year: 2021/2022 Supervisor: Mrázek Vojtěch, Ing., Ph.D.
English title
Approximation of Digital Circuits in Yosys Tool

The goal of this work is introduction of cgploss extension. This extension is extension for combinational logic circuits optimization in Yosys tool. Cartesian genetic programming is introduced in the first part of this work. Cartesian genetic programming is a design and optimization method that can be used for circuit optimization and approximation. This chapter introduces representation of combinational logic circuits for Cartesian genetic programming. The next chapter introduces Yosys tool and possibilities of the Yosys extending. The proposed 'cgploss' extension is introduced in the next chapter. The chapter also provides details about the implementation and the usage. The last chapter tests cgploss extension and compares representation of combinational logic circuits.


combinational circuit, optimization, combinational circuits optimization, logic gate, Cartesian genetic programming, CGP, AIG, MIG, logic gates representation, And-inverter graph, Majority-Inverter Graph, Yosys, Verilog

Degree Programme
defended, grade C
14 June 2022
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT), předseda
Hradiš Michal, Ing., Ph.D. (DCGM FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Křivka Zbyněk, Ing., Ph.D. (DIFS FIT BUT), člen
Lengál Ondřej, Ing., Ph.D. (DITS FIT BUT), člen
PLEVAČ, Lukáš. Aproximace obvodů v nástroji Yosys. Brno, 2022. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2022-06-14. Supervised by Mrázek Vojtěch. Available from:
    author = "Luk\'{a}\v{s} Pleva\v{c}",
    type = "Bachelor's thesis",
    title = "Aproximace obvod\r{u} v n\'{a}stroji Yosys",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2022,
    location = "Brno, CZ",
    language = "czech",
    url = ""
Back to top