Thesis Details
Paměťový subsystém v SystemC
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
SystemC, TLM, abstract processor model, processor simulation, Codasip, Codasip studio, Codasip simulator, bus, AHB3-lite, AXI4-lite, CPB, CPB-lite
Bidlo Michal, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Češka Milan, doc. RNDr., Ph.D. (DITS FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Kekely Lukáš, Ing., Ph.D. (DCSY FIT BUT), člen
Martínek Tomáš, doc. Ing., Ph.D. (DCSY FIT BUT), člen
@mastersthesis{FITMT22495,
author = "Kamil Michl",
type = "Master's thesis",
title = "Pam\v{e}\v{t}ov\'{y} subsyst\'{e}m v SystemC",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2020,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/22495/"
}