Thesis Details
Hardwarová akcelerace extrakce a spojování položek z hlaviček paketů
Almost every device on the network needs to extract some fields from the packet headers for its operation, perform operations on them, and forward the reassembled packet. This processing must be implemented at a speed corresponding to the line speed. On high-speed networks, specialized circuits are used to meet this requirement. As the demands on network flexibility increase, so do the demands on the flexibility of these circuits. However, making changes to the hardware description languages is complex and time consuming. This work therefore deals with the implementation of circuits for extraction and subsequent merging of packet header items using high-level synthesis.
HLS, FPGA, Extraction, Merging, Internet traffic
Hradiš Michal, Ing., Ph.D. (DCGM FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Křivka Zbyněk, Ing., Ph.D. (DIFS FIT BUT), člen
Lengál Ondřej, Ing., Ph.D. (DITS FIT BUT), člen
@bachelorsthesis{FITBT23902,
author = "Mikul\'{a}\v{s} Br\'{a}zda",
type = "Bachelor's thesis",
title = "Hardwarov\'{a} akcelerace extrakce a spojov\'{a}n\'{i} polo\v{z}ek z hlavi\v{c}ek paket\r{u}",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2022,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/23902/"
}