Thesis Details
Prostředí pro funkční verifikaci multi-sběrnic podle UVM standardu
This thesis focus on the design and subsequent implementation of a multi-bus verification environment using the principles of the Universal Verification Methodology (UVM). It also focus on the implementation of the verification of three FPGA components using multi-bus as input and output interfaces. The implementation of the environment and all verifications is written in SystemVerilog language using a library that implement the basic constructs for UVM. The achieved results of the work are functional and easily reusable when creating further verifications using multi-bus. The proposed environments can be used as a structure for creating other verification environments for other buses.
UVM, Verification, Functional verification, FPGA, Multi buses
Hliněná Dana, doc. RNDr., Ph.D. (DMAT FEEC BUT), člen
Hradiš Michal, Ing., Ph.D. (DCGM FIT BUT), člen
Polčák Libor, Ing., Ph.D. (DIFS FIT BUT), člen
Šátek Václav, Ing., Ph.D. (DITS FIT BUT), člen
@bachelorsthesis{FITBT24972, author = "Tom\'{a}\v{s} Bene\v{s}", type = "Bachelor's thesis", title = "Prost\v{r}ed\'{i} pro funk\v{c}n\'{i} verifikaci multi-sb\v{e}rnic podle UVM standardu", school = "Brno University of Technology, Faculty of Information Technology", year = 2022, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/24972/" }