Thesis Details
Návrh testeru paměti RAM ve VHDL
This paper describes various approaches to hardware testing semiconductor memory. We describe the priciple of basic memory types, the way which each of them stores information and their comunication protocol. Following part deals with common failures which may occur in the memory. The section also describes the implementation of memory model and tester designed in VHDL language. It is possible to inject some errors into memory, which are later detected by the tester. The final section shows the response of tester to various error types according to used error detection method. The paper is especially focused on failure detection by variants of march test.
Test, memory, RAM, memory cell, SRAM, DRAM, static memory, dynamic memory, error, march test, address decoder.
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Kolář Dušan, doc. Dr. Ing. (DIFS FIT BUT), člen
Křena Bohuslav, Ing., Ph.D. (DITS FIT BUT), člen
Motyčka Arnošt, doc. Ing., CSc. (Mendelu), člen
Ráb Jaroslav, Ing. (DIFS FIT BUT), člen
@mastersthesis{FITMT6182,
author = "Ji\v{r}\'{i} Charv\'{a}t",
type = "Master's thesis",
title = "N\'{a}vrh testeru pam\v{e}ti RAM ve VHDL",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2007,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/6182/"
}