Faculty of Information Technology, BUT

Publication Details

FPGA Prototyping and Accelerated Verification of ASIPs

PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela, ČEKAN Ondřej and KOTÁSEK Zdeněk. FPGA Prototyping and Accelerated Verification of ASIPs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, pp. 145-148. ISBN 978-1-4799-6779-7.
Czech title
Prototypování a akcelerace verifikace ASIP procesorů pomocí FPGA
Type
conference paper
Language
english
Authors
Keywords
UVM, Acceleration, FPGA Prototyping, ASIP
Abstract
In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.
Published
2015
Pages
145-148
Proceedings
IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, RS
ISBN
978-1-4799-6779-7
Publisher
IEEE Computer Society
Place
Belgrade, RS
BibTeX
@INPROCEEDINGS{FITPUB10881,
   author = "Jakub Podiv\'{i}nsk\'{y} and Marcela Zachari\'{a}\v{s}ov\'{a} and Ond\v{r}ej \v{C}ekan and Zden\v{e}k Kot\'{a}sek",
   title = "FPGA Prototyping and Accelerated Verification of ASIPs",
   pages = "145--148",
   booktitle = "IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2015,
   location = "Belgrade, RS",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4799-6779-7",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10881"
}
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