Faculty of Information Technology, BUT

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Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

SÁNCHEZ-CLEMENTE Antonio José, ENTRENA Luis, HRBÁČEK Radek and SEKANINA Lukáš. Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1871-1883. ISSN 0018-9529. Available from: http://dx.doi.org/10.1109/TR.2016.2604918
Czech title
Maskování chyb pomocí aproximovaných logických obvodů: Porovnání pravděpodobnostního a evolučního přístupu
Type
journal article
Language
english
Authors
Sánchez-Clemente Antonio José (UC3M)
Entrena Luis (UC3M)
Hrbáček Radek, Ing. (DCSY FIT BUT)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)
URL
Keywords

Approximate logic circuit, error mitigation, evolutionary computing, single-event transient (SET), single-event upset (SEU)
Abstract
Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.
Published
2016
Pages
1871-1883
Journal
IEEE Transactions on Reliability, vol. 65, no. 4, ISSN 0018-9529
Publisher
Institute of Electrical and Electronics Engineers
DOI
BibTeX
@ARTICLE{FITPUB10995,
   author = "Jos\'{e} Antonio S\'{a}nchez-Clemente and Luis Entrena and Radek Hrb\'{a}\v{c}ek and Luk\'{a}\v{s} Sekanina",
   title = "Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches",
   pages = "1871--1883",
   journal = "IEEE Transactions on Reliability",
   volume = 65,
   number = 4,
   year = 2016,
   ISSN = "0018-9529",
   doi = "10.1109/TR.2016.2604918",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10995"
}
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