Publication Details

Input and Output Generation for the Verification of ALU: a Use Case

ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 331-336. ISBN 978-1-5386-5709-6.
Czech title
Generování vstupů a výstupů pro verifikaci ALU
Type
conference paper
Language
english
Authors
Čekan Ondřej, Ing. (DCSY FIT BUT)
Pánek Richard, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords
Stimuli generation, arithmetic logic unit, probabilistic constrained grammar, functional verification
Abstract
The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.
Published
2018
Pages
331-336
Proceedings
Proceedings of IEEE East-West Design & Test Symposium
Conference
16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM, Kazan, RU
ISBN
978-1-5386-5709-6
Publisher
IEEE Computer Society
Place
Kazan, RU
DOI
BibTeX
@INPROCEEDINGS{FITPUB11833,
   author = "Ond\v{r}ej \v{C}ekan and Richard P\'{a}nek and Zden\v{e}k Kot\'{a}sek",
   title = "Input and Output Generation for the Verification of ALU: a Use Case",
   pages = "331--336",
   booktitle = "Proceedings of IEEE East-West Design \& Test Symposium",
   year = 2018,
   location = "Kazan, RU",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-5386-5709-6",
   doi = "10.1109/EWDTS.2018.8524641",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11833"
}
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