Publication Details

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš and KOTÁSEK Zdeněk. Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. In: Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019, pp. 597-600. ISBN 978-1-7281-2861-0.
Czech title
Případová studie výpočtu průniku multidimenzionálních Pareto front v optimalizaci procesoru
Type
conference paper
Language
english
Authors
Keywords

Pareto optimization, Pareto frontier, processor optimization, ASIP.

Abstract

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Published
2019
Pages
597-600
Proceedings
Proceedings of the 2019 22nd Euromicro Conference on Digital System Design
Conference
22nd Euromicro Conference on Digital Systems Design, Athos Palace Hotel, Solinas, Kalithea, 63077 Chalkidiki, GR
ISBN
978-1-7281-2861-0
Publisher
Institute of Electrical and Electronics Engineers
Place
Kalithea, GR
DOI
EID Scopus
BibTeX
@INPROCEEDINGS{FITPUB11967,
   author = "Jakub Podiv\'{i}nsk\'{y} and Ond\v{r}ej \v{C}ekan and Martin Kr\v{c}ma and Radek Burget and Tom\'{a}\v{s} Hru\v{s}ka and Zden\v{e}k Kot\'{a}sek",
   title = "Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study",
   pages = "597--600",
   booktitle = "Proceedings of the 2019 22nd Euromicro Conference on Digital System Design",
   year = 2019,
   location = "Kalithea, GR",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-7281-2861-0",
   doi = "10.1109/DSD.2019.00091",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11967"
}
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