Publication Details

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

KLHŮFEK Jan and MRÁZEK Vojtěch. ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. In: 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague: Institute of Electrical and Electronics Engineers, 2022, pp. 44-47. ISBN 978-1-6654-9431-1. Available from: https://doi.org/10.1109/DDECS54261.2022.9770152

Czech title

ArithsGen: Generátor aritmetických obvodů použitelných v hardwarových akcelerátorech

Type

conference paper

Language

english

Authors

Klhůfek Jan, Bc. (FIT BUT)
Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)

URL

https://doi.org/10.1109/DDECS54261.2022.9770152

Keywords

arithmetic circuit, generator, verilog, verification, approximate computing

Published

2022

Pages

44-47

Proceedings

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)

Conference

25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Hotel Vienna House Diplomat Prague, Evropská 370/15, 160 41 Praha 6, CZ

ISBN

978-1-6654-9431-1

Publisher

Institute of Electrical and Electronics Engineers

Place

Prague, CZ

DOI

10.1109/DDECS54261.2022.9770152

UT WoS

000835725500008

EID Scopus

2-s2.0-85130500895

BibTeX

@INPROCEEDINGS{FITPUB12570,
   author = "Jan Klh\r{u}fek and Vojt\v{e}ch Mr\'{a}zek",
   title = "ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators",
   pages = "44--47",
   booktitle = "2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)",
   year = 2022,
   location = "Prague, CZ",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-6654-9431-1",
   doi = "10.1109/DDECS54261.2022.9770152",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/12570"
}