RT Level Testability Analysis to Reduce Test Application Time

The paper describes the research activities the goal of which is to develop a methodology that solves the problem of the RT level testability analysis in a complex way. On the basis of the RT level testability analysis the reduction in test application time can be achieved. A new model of RT level elements classification for the purposes of the RT level testability analysis is described. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described.