Result Details

Test Scheduling for SOC under Power Constraints

ŠKARVADA, J. Test Scheduling for SOC under Power Constraints. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 91-93. ISBN: 1-4244-0184-4.
Type
conference paper
Language
English
Authors
Škarvada Jaroslav, Ing., Ph.D., DCSY (FIT)
Abstract

The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.

Keywords

test scheduling, power constraint, test application conflict graph, genetic algorithm

Published
2006
Pages
91–93
Proceedings
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
ISBN
1-4244-0184-4
Publisher
Czech Technical University Publishing House
Place
Prague
BibTeX 
@inproceedings{BUT22187,
  author="Jaroslav {Škarvada}",
  title="Test Scheduling for SOC under Power Constraints",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2006",
  pages="91--93",
  publisher="Czech Technical University Publishing House",
  address="Prague",
  isbn="1-4244-0184-4"
}
Projects
Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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