Detail výsledku

Test Scheduling for SOC under Power Constraints

ŠKARVADA, J. Test Scheduling for SOC under Power Constraints. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 91-93. ISBN: 1-4244-0184-4.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Škarvada Jaroslav, Ing., Ph.D., FIT (FIT), UPSY (FIT)
Abstrakt

The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.

Klíčová slova

test scheduling, power constraint, test application conflict graph, genetic algorithm

Rok
2006
Strany
91–93
Sborník
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Konference
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
ISBN
1-4244-0184-4
Vydavatel
Czech Technical University Publishing House
Místo
Prague
BibTeX 
@inproceedings{BUT22187,
  author="Jaroslav {Škarvada}",
  title="Test Scheduling for SOC under Power Constraints",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2006",
  pages="91--93",
  publisher="Czech Technical University Publishing House",
  address="Prague",
  isbn="1-4244-0184-4"
}
Projekty
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru