Result Details

Formal Model of Testable Block

HERRMAN, T. Formal Model of Testable Block. Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006. p. 451-455. ISBN: 80-214-3163-6.

Type

conference paper

Language

English

Authors

Herrman Tomáš, Ing., Ph.D., DCSY (FIT)

Abstract

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

Keywords

RT level, Testable block, formal model, scan chain

Published

2006

Pages

451–455

Proceedings

Proceedings of 12th Conference Student EEICT 2006, Volume 4

Conference

Student EEICT 2006

ISBN

80-214-3163-6

Publisher

Faculty of Electrical Engineering and Communication BUT

Place

Brno

BibTeX

@inproceedings{BUT22191,
  author="Tomáš {Herrman}",
  title="Formal Model of Testable Block",
  booktitle="Proceedings of 12th Conference Student EEICT 2006, Volume 4",
  year="2006",
  pages="451--455",
  publisher="Faculty of Electrical Engineering and Communication BUT",
  address="Brno",
  isbn="80-214-3163-6",
  url="https://www.fit.vut.cz/research/publication/8051/"
}

Files

doc Formální model testovatelného bloku - článek 84 kB

Projects

Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed

Research groups

Dependable Digital Systems Research Group (RG DEPSYS)

Departments

Department of Computer Systems (DCSY)