Result Details

Testability Analysis Based on Formal Model

HERRMAN, T. Testability Analysis Based on Formal Model. Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006. p. 243-248. ISBN: 80-8073-598-0.
Type
conference paper
Language
English
Authors
Herrman Tomáš, Ing., Ph.D., DCSY (FIT)
Abstract

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

Keywords

formal model, RT level, testable block, testability analysis

Published
2006
Pages
243–248
Proceedings
Proceedings of the Sevnth International Scientific Conference ECI 2006
Conference
7TH International Scientific Conference Electronic Computers and Informatics 2006
ISBN
80-8073-598-0
Publisher
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Place
Košice
BibTeX 
@inproceedings{BUT22268,
  author="Tomáš {Herrman}",
  title="Testability Analysis Based on Formal Model",
  booktitle="Proceedings of the Sevnth International Scientific Conference ECI 2006",
  year="2006",
  pages="243--248",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0"
}
Projects
Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
Back to top