Detail výsledku

Testability Analysis Based on Formal Model

HERRMAN, T. Testability Analysis Based on Formal Model. Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006. p. 243-248. ISBN: 80-8073-598-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Herrman Tomáš, Ing., Ph.D., UPSY (FIT)
Abstrakt

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

Klíčová slova

formal model, RT level, testable block, testability analysis

Rok
2006
Strany
243–248
Sborník
Proceedings of the Sevnth International Scientific Conference ECI 2006
Konference
7TH International Scientific Conference Electronic Computers and Informatics 2006
ISBN
80-8073-598-0
Vydavatel
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Místo
Košice
BibTeX 
@inproceedings{BUT22268,
  author="Tomáš {Herrman}",
  title="Testability Analysis Based on Formal Model",
  booktitle="Proceedings of the Sevnth International Scientific Conference ECI 2006",
  year="2006",
  pages="243--248",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0"
}
Projekty
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru