Result Details

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

ŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z. RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool. IEEE 8th Workshop on RTL and High Level Testing. Beijing: Institute of Computing Technology, Chinese Academy of Sciences, 2007. p. 175-181.
Type
conference paper
Language
English
Authors
Škarvada Jaroslav, Ing., Ph.D., DCSY (FIT)
Herrman Tomáš, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

Keywords

Testable block, power consumption estimation, test vectors generation, power consumption optimization.

URL
Published
2007
Pages
175–181
Proceedings
IEEE 8th Workshop on RTL and High Level Testing
Conference
IEEE 8th Workshop on RTL and High Level Testing
Publisher
Institute of Computing Technology, Chinese Academy of Sciences
Place
Beijing
BibTeX 
@inproceedings{BUT26071,
  author="Jaroslav {Škarvada} and Tomáš {Herrman} and Zdeněk {Kotásek}",
  title="RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool",
  booktitle="IEEE 8th Workshop on RTL and High Level Testing",
  year="2007",
  pages="175--181",
  publisher="Institute of Computing Technology, Chinese Academy of Sciences",
  address="Beijing",
  url="https://www.fit.vut.cz/research/publication/8487/"
}
Files
Projects
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
Back to top