Thesis Details

Vizualizace práce CPU

Bachelor's Thesis Student: Ďurčo Marián Academic Year: 2016/2017 Supervisor: Vojnar Tomáš, prof. Ing., Ph.D.
English title
Visualising CPU Activity
Language
Czech
Abstract

This thesis is intended to be a complement for learning about the RISC pipeline. Product of this thesis is a web application. After reviewing various tools and libraries suitable for this work, we have chosen two main libraries React and Redux. The created solution allows the instruction flow to be displayed in the RISC pipeline as well as states of the registers and the memory. It makes easy to perform transitions between the various parts of the visualization. This visualization allows a basic understanding of the RISC pipeline principles and also individual assembly instructions.

Keywords

RISC, visualisation, pipelining, pipeline, asembler, web applications, SPA, React, Redux

Department
Degree Programme
Files
Status
defended, grade C
Date
16 June 2017
Reviewer
Committee
Vojnar Tomáš, prof. Ing., Ph.D. (DITS FIT BUT), předseda
Grézl František, Ing., Ph.D. (DCGM FIT BUT), člen
Hanáček Petr, doc. Dr. Ing. (DITS FIT BUT), člen
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Veselý Vladimír, Ing., Ph.D. (DIFS FIT BUT), člen
Citation
ĎURČO, Marián. Vizualizace práce CPU. Brno, 2017. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2017-06-16. Supervised by Vojnar Tomáš. Available from: https://www.fit.vut.cz/study/thesis/19853/
BibTeX
@bachelorsthesis{FITBT19853,
    author = "Mari\'{a}n \v{D}ur\v{c}o",
    type = "Bachelor's thesis",
    title = "Vizualizace pr\'{a}ce CPU",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2017,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/19853/"
}
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