Publication Details

Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study

STRNADEL Josef and RAJNOHA Peter. Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study. Acta Electrotechnica et Informatica, vol. 12, no. 4, 2012, pp. 17-29. ISSN 1335-8243.
Czech title
Reflektování modelu RTOS při WCET analýze: Případová studie pro MSP430/FreeRTOS
Type
journal article
Language
english
Authors
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT)
Rajnoha Peter, Ing. (FIT BUT)
URL
Keywords

analysis, assembly, compiler, FreeRTOS, model, MSPsim, MSP430, operating system, profiler, real time, response time, simulator, worst case, execution time

Abstract

The determination of the execution time upper bound, commonly called Worst-Case Execution Time (WCET), is a necessary step in the development and validation process for real-time systems. The WCET analysis techniques can be classified as static or dynamic. While a high-level language code suffices for the static techniques, for a precise WCET analysis a target architecture or its authentic simulator able to run the final machine-level code of an analyzed application is needed by the dynamic techniques. In the paper, we have decided not only to present a novel hybrid timing analysis technique, but also to show its practical applicability in the area of WCET analysis over particular embedded architecture (MSP430) and real-time operating system (FreeRTOS). Novelty of the presented method can be seen in the fact the operating system model is reflected during the analysis in order to facilitate the process of derivating schedulability test formulas, create detail task/stack analysis etc. Applicability of the method was tested using the MSPsim simulator of the MSP430 architecture.

Published
2012
Pages
17-29
Journal
Acta Electrotechnica et Informatica, vol. 12, no. 4, ISSN 1335-8243
DOI
BibTeX
@ARTICLE{FITPUB10250,
   author = "Josef Strnadel and Peter Rajnoha",
   title = "Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study",
   pages = "17--29",
   journal = "Acta Electrotechnica et Informatica",
   volume = 12,
   number = 4,
   year = 2012,
   ISSN = "1335-8243",
   doi = "10.2478/v10198-012-0041-3",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10250"
}
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