Faculty of Information Technology, BUT

Publication Details

Decreasing Test Time by Scan Chain Reorganization

BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 371-374. ISBN 978-1-4244-9753-9.
Czech title
Zkracování doby aplikace testu přeuspořádáním scan řetězce
Type
conference paper
Language
english
Authors
Bartoš Pavel, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Dohnal Jan, Ing., Ph.D. (ONDESIGN)
Keywords
scan chain, test, time, reordering, reorganization, physical, layout
Abstract
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.
Published
2011
Pages
371-374
Proceedings
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011, Cottbus, DE
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus, DE
BibTeX
@INPROCEEDINGS{FITPUB9556,
   author = "Pavel Barto\v{s} and Zden\v{e}k Kot\'{a}sek and Jan Dohnal",
   title = "Decreasing Test Time by Scan Chain Reorganization",
   pages = "371--374",
   booktitle = "IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
   year = 2011,
   location = "Cottbus, DE",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4244-9753-9",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9556"
}
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