Thesis Details

Úkázky hardwarové akcelerace na přípravku Pynq Z2

Master's Thesis Student: Vosyka Pavel Academic Year: 2021/2022 Supervisor: Kořenek Jan, doc. Ing., Ph.D.
English title
Hardware Acceleration Demo on the Pynq Z2 Board
Language
Czech
Abstract

The work deals with a hardware acceleration on the Zynq platform with Pynq technology. Three examples demonstrating hardware acceleration were designed for teaching purposes. The effort was to make examples as simple as possible to make them  easy to understand. Hardware accelerators are implemented in VHDL language and driven by implemented Python application. The examples were successfully implemented and evaluated.

Keywords

Hardware acceleration, Pynq, Pynq Z2, Zynq, Xilinx

Department
Degree Programme
Files
Status
defended, grade E
Date
17 June 2022
Reviewer
Committee
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Lengál Ondřej, Ing., Ph.D. (DITS FIT BUT), člen
Martínek Tomáš, Ing., Ph.D. (DCSY FIT BUT), člen
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT), člen
Citation
VOSYKA, Pavel. Úkázky hardwarové akcelerace na přípravku Pynq Z2. Brno, 2022. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2022-06-17. Supervised by Kořenek Jan. Available from: https://www.fit.vut.cz/study/thesis/25156/
BibTeX
@mastersthesis{FITMT25156,
    author = "Pavel Vosyka",
    type = "Master's thesis",
    title = "\'{U}k\'{a}zky hardwarov\'{e} akcelerace na p\v{r}\'{i}pravku Pynq Z2",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2022,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/25156/"
}
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