Detail výsledku

Automatic Construction of On-line Checking Circuits Based on Finite Automata

MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 326-332. ISBN: 978-0-7695-5074-9.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Matušová Lucie, Ing.
Kaštil Jan, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper
proves that it is possible to automatically generate the model
for the online checker which describes the basic behaviour of
the checked component. The obtained checker is up to six times
smaller than the original component.

Klíčová slova


Fault Tolerant,Active Automata Learning,Online Checkers,Mealy Machine

Rok
2014
Strany
326–332
Sborník
17th Euromicro Conference on Digital Systems Design
Konference
17th Euromicro Conference on Digital Systems Design: Architectures, Methods and Tools
ISBN
978-0-7695-5074-9
Vydavatel
IEEE Computer Society
Místo
Verona
DOI
10.1109/DSD.2014.78
UT WoS
000358409000043
EID Scopus
2-s2.0-84928786780
BibTeX 
@inproceedings{BUT111659,
  author="Lucie {Matušová} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Automatic Construction of On-line Checking Circuits Based on Finite Automata",
  booktitle="17th Euromicro Conference on Digital Systems Design",
  year="2014",
  pages="326--332",
  publisher="IEEE Computer Society",
  address="Verona",
  doi="10.1109/DSD.2014.78",
  isbn="978-0-7695-5074-9"
}
Projekty
Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace, MŠMT, COST CZ (2011-2017), LD12036, zahájení: 2012-03-01, ukončení: 2015-11-30, ukončen
Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace, MŠMT, COST, COST IC1103, zahájení: 2011-06-15, ukončení: 2015-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru