Detail výsledku
Mapping of P4 Match Action Tables to FPGA
KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. p. 1-2. ISBN: 978-90-90-30428-1.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kekely Michal, Ing., Ph.D., UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt
Current networks are changing very fast. Network
administrators need
more flexible and powerful tools to be able to
support new protocols or services very fast. The P4 language
provides new level of abstraction for flexible packet processing.
Therefore, we have designed new architecture for memory
efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance
the processing speed and available memory resources.
support new protocols or services very fast. The P4 language
provides new level of abstraction for flexible packet processing.
Therefore, we have designed new architecture for memory
efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance
the processing speed and available memory resources.
Klíčová slova
P4, FPGA, packet classification, match action tables
Rok
2017
Strany
1–2
Sborník
Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
Konference
27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
ISBN
978-90-90-30428-1
Vydavatel
Institute of Electrical and Electronics Engineers
Místo
Ghent
DOI
UT WoS
000426989400013
EID Scopus
BibTeX
@inproceedings{BUT144482,
author="Michal {Kekely} and Jan {Kořenek}",
title="Mapping of P4 Match Action Tables to FPGA",
booktitle="Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS",
year="2017",
pages="1--2",
publisher="Institute of Electrical and Electronics Engineers",
address="Ghent",
doi="10.23919/FPL.2017.8056768",
isbn="978-90-90-30428-1"
}
Projekty
Pokročilé paralelní a vestavěné počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-17-3994, zahájení: 2017-03-01, ukončení: 2020-02-29, ukončen
Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů, MV, Bezpečnostní výzkum České republiky 2015-2020, VI20152019001, zahájení: 2015-09-01, ukončení: 2019-05-31, ukončen
Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů, MV, Bezpečnostní výzkum České republiky 2015-2020, VI20152019001, zahájení: 2015-09-01, ukončení: 2019-05-31, ukončen
Pracoviště
Ústav počítačových systémů
(UPSY)