Detail výsledku
Test Controller Design Based on VHDL Source File Analysis
MIKA, D.; KOTÁSEK, Z.; STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Mika Daniel, Ing., Ph.D., FIT (FIT)
Kotásek Zdeněk, doc. Ing., CSc.
Strnadel Josef, Ing., Ph.D., FIT (FIT)
Kotásek Zdeněk, doc. Ing., CSc.
Strnadel Josef, Ing., Ph.D., FIT (FIT)
Abstrakt
In the paper the process of test controller design and synthesis onregister transfer level (RTL) is described. The sequence of control,address and data signals together with circuit structure for which thetest controller is designed are the input information of the problem.The methodology of transforming an RTL circuit into a labelled directedgraph and then into VHDL source code will be presented. The ideas oftest controller synthesis based on this information will be explicitlyshown.
Klíčová slova
Register Transfer Level, Data Transporter, Data Processor, The Unit Under Analysis
Rok
2002
Strany
135–141
Sborník
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
Řada
VIENALA Press, Edition: 55
Konference
Electronic Computers and Informatics'2002
ISBN
80-7099-879-2
Vydavatel
The University of Technology Košice
Místo
Letná 42, 040 01 TU Košice
BibTeX
@inproceedings{BUT10249,
author="Daniel {Mika} and Zdeněk {Kotásek} and Josef {Strnadel}",
title="Test Controller Design Based on VHDL Source File Analysis",
booktitle="Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002",
year="2002",
series="VIENALA Press, Edition: 55",
pages="135--141",
publisher="The University of Technology Košice",
address="Letná 42, 040 01 TU Košice",
isbn="80-7099-879-2"
}
Projekty
Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu, GAČR, Standardní projekty, GA102/01/1531, zahájení: 2001-01-01, ukončení: 2003-12-31, ukončen
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