Detail výsledku
Methodology of Selecting Scan-Based Testability Improving Technique
        KOTÁSEK, Z.; STRNADEL, J.; PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 186-189.  ISBN: 963-9364-48-7.
    
                Typ
            
        
                článek ve sborníku konference
            
        
                Jazyk
            
        
                anglicky
            
        
            Autoři
            
        
                Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
                
Strnadel Josef, Ing., Ph.D., UPSY (FIT)
Pečenka Tomáš, Ing., Ph.D., FIT (FIT), UPSY (FIT)
        Strnadel Josef, Ing., Ph.D., UPSY (FIT)
Pečenka Tomáš, Ing., Ph.D., FIT (FIT), UPSY (FIT)
                    Abstrakt
            
        In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.
                Klíčová slova
            
        design for testability, scan method, testable core
                URL
            
        
                Rok
            
            
                    2005
                    
                
            
                    Strany
                
            
                        186–189
                
            
                        Sborník
                
            
                    Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
                
            
                    Konference
                
            
                    IEEE Design and Diagnostics of Electronic Circuits and systems (DDECS'06)
                    
The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
            The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
                    ISBN
                
            
                    963-9364-48-7
                
            
                    Vydavatel
                
            
                    University of West Hungary
                
            
                    Místo
                
            
                    Sopron
                
            
                    BibTeX
                
            @inproceedings{BUT21466,
  author="Zdeněk {Kotásek} and Josef {Strnadel} and Tomáš {Pečenka}",
  title="Methodology of Selecting Scan-Based Testability Improving Technique",
  booktitle="Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  year="2005",
  pages="186--189",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="963-9364-48-7",
  url="http://www.fit.vutbr.cz/~pecenka/pubs/2005_ddecs_scan.pdf"
}
                Projekty
            
        
        
            
        
    
    
        Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
            
        
                Výzkumné skupiny
            
        
                Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
            
        
                Pracoviště
            
        
                Ústav počítačových systémů 
                (UPSY)