Detail výsledku

DSP/FPGA Embedded Image Processing Accelerator Harnessed in Traffic Monitoring

HEROUT, A.; ZEMČÍK, P. DSP/FPGA Embedded Image Processing Accelerator Harnessed in Traffic Monitoring. Proceedings of the IWES 2006 Workshop. Heraklion: 2006. 1 p.
Typ
abstrakt
Jazyk
anglicky
Autoři
Herout Adam, prof. Ing., Ph.D., UPGM (FIT)
Zemčík Pavel, prof. Dr. Ing., dr. h. c., UPGM (FIT)
Abstrakt

This contribution presents overall information about a traffic monitoring system based on image processing which employs an embedded image processing accelerator board. The system uses a set of spatially distributed sensors and video acquisition units interconnected by a computer network (both wired and wireless). The system provides means of traffic rules enforcement as well as gathering of statistical information about the traffic flow and also detects non-standard situations such as traffic jams. Several cities in the Czech Republic use this system to cope with the challenges of contemporary traffic.

Klíčová slova

image processing, embedded processing, DSP, FPGA, traffic monitoring

Rok
2006
Strany
1
Kniha
Proceedings of the IWES 2006 Workshop
Místo
Heraklion
BibTeX 
@misc{BUT192617,
  author="Adam {Herout} and Pavel {Zemčík}",
  title="DSP/FPGA Embedded Image Processing Accelerator Harnessed in Traffic Monitoring",
  booktitle="Proceedings of the IWES 2006 Workshop",
  year="2006",
  pages="1",
  address="Heraklion",
  note="Abstract"
}
Pracoviště
Ústav počítačové grafiky a multimédií (UPGM)
Nahoru