Detail výsledku
VHDL Design of Educational, Modern and Open-Architecture CPU
The paper deals with design of a modern, open-architecture CPU utilizable for educational
purposes. It is expected that use of the CPU in the educational process will greatly contribute
to deeper understanding of key-topics taught in the area of modern architectures. Our
CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache
memory unit and simple branch prediction unit. The architecture is designed in VHDL including
set of 16 instructions. Rich variety of educative tasks can be performed by means
of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision
RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real
working CPU.
VHDL, pipeline, CPU, cache, prediction unit
@inproceedings{BUT28605,
author="Martin {Straka}",
title="VHDL Design of Educational, Modern and Open-Architecture CPU",
booktitle="Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4",
year="2007",
pages="457--461",
publisher="Brno University of Technology",
address="Brno",
isbn="978-80-214-3410-3",
url="https://www.fit.vut.cz/research/publication/8339/"
}Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení