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Digital Systems Architectures Based on On-line Checkers

STRAKA Martin, KOTÁSEK Zdeněk a WINTER Jan. Digital Systems Architectures Based on On-line Checkers. In: 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008, s. 81-87. ISBN 978-0-7695-3277-6.
Název česky
Digital Systems Architectures Based on On-line Checkers
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Abstrakt
In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented.
Rok
2008
Strany
81-87
Sborník
11th EUROMICRO Conference on Digital System Design DSD 2008
Konference
11th EUROMICRO Conference on Digital Systems Design 2008, Parma, IT
ISBN
978-0-7695-3277-6
Vydavatel
IEEE Computer Society
Místo
Parma, IT
BibTeX
@INPROCEEDINGS{FITPUB8621,
   author = "Martin Straka and Zden\v{e}k Kot\'{a}sek and Jan Winter",
   title = "Digital Systems Architectures Based on On-line Checkers",
   pages = "81--87",
   booktitle = "11th EUROMICRO Conference on Digital System Design DSD 2008",
   year = 2008,
   location = "Parma, IT",
   publisher = "IEEE Computer Society",
   ISBN = "978-0-7695-3277-6",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8621"
}
Soubory
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