Detail výsledku

I-path Scheduling Algorithm for RT Level Circuits

PEČENKA, T.; KOTÁSEK, Z. I-path Scheduling Algorithm for RT Level Circuits. MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov: 2006. p. 174-181. ISBN: 80-214-3287-X.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Pečenka Tomáš, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

In the paper, a new approach for scheduling i-paths in Register Transfer (RT) level circuits is presented. The proposed algorithm is able to schedule i-paths not only in circuit structure, but also in time. At the beginning, the formal model for modelling data-path of structurally described RT level circuits is defined. This model is then used to define the i-path concept. The main part of the paper is devoted to introduce a method for i-path scheduling. The method is able to monitor component utilization in time and it is able to detect and solve conflicts between i-paths.

Klíčová slova

i-path, scheduling, backtracking

Rok
2006
Strany
174–181
Sborník
MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Konference
2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science -- MEMICS'06
ISBN
80-214-3287-X
Místo
Mikulov
BibTeX 
@inproceedings{BUT22284,
  author="Tomáš {Pečenka} and Zdeněk {Kotásek}",
  title="I-path Scheduling Algorithm for RT Level Circuits",
  booktitle="MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2006",
  pages="174--181",
  address="Mikulov",
  isbn="80-214-3287-X"
}
Projekty
Integrovaný přístup k výchově studentů DSP v oblasti paralelních a distribuovaných systémů, GAČR, Doktorské granty, GD102/05/H050, zahájení: 2005-01-01, ukončení: 2008-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru