Ing.

Aleš Smrčka

Ph.D.

Odborný asistent

+420 54114 1186
smrcka@fit.vut.cz
Kancelář A304

[photo]

Publikace

  • 2020

    BARBOSA Raul, BECKER Hauke, ESNAOLA Mikel L., FERRARI Enrico, FOLKESSON Peter, GIANTAMIDIS Georgios, KANAK Alper, PEREIRA David M., POMANTE Luigi, SANGCHOOLIE Behrooz, SCHLICK Rupert, SMRČKA Aleš a YAZICI Ahmed. The VALU3S ECSEL Project: Verification and Validation of Automated Systems Safety and Security. In: 2020 23rd Euromicro Conference on Digital System Design (DSD). Krajn: Institute of Electrical and Electronics Engineers, 2020, s. 115-129. ISBN 978-1-7281-9535-3.
    Detail

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Utilizing parametric systems for detection of pipeline hazards. International Journal on Software Tools for Technology Transfer, roč. 2020, č. 1, s. 1-28. ISSN 1433-2779.
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  • 2018

    FIEDOR Jan, MUŽIKOVSKÁ Monika, SMRČKA Aleš, VAŠÍČEK Ondřej a VOJNAR Tomáš. Advances in the ANaConDA Framework for Dynamic Analysis and Testing of Concurrent C/C++ Programs. In: Proceedings of 27th ACM SIGSOFT International Symposium on Software Testing and Analysis. New York: Association for Computing Machinery, 2018, s. 356-359. ISBN 978-1-4503-5699-2.
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  • 2017

    DIAS Ricardo J., FERREIRA Carla, FIEDOR Jan, LOURENCO Joao, SMRČKA Aleš, SOUSA Diogo J. a VOJNAR Tomáš. Verifying Concurrent Programs Using Contracts. In: 2017 IEEE International Conference on Software Testing, Verification and Validation (ICST). Tokyo: Institute of Electrical and Electronics Engineers, 2017, s. 196-206. ISBN 978-1-5090-6032-0.
    Detail

  • 2016

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Hades: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. In: Proceedings 11th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2016). Electronic Proceedings in Theoretical Computer Science, roč. 2016. Brno: Fakulta informatiky MU, 2016, s. 87-93. ISBN 978-80-210-8362-2. ISSN 2075-2180.
    Detail

  • 2015

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. In: Proceedings of the 15th International Conference on Computer Aided Systems Theory (EUROCAST 2015). Las Palmas de Grand Canaria: Universidad de Las Palmas de Gran Canaria, 2015, s. 193-194. ISBN 978-84-606-5438-4.
    Detail

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Microprocessor Hazard Analysis Via Formal Verification of Parameterized Systems. In: Computer Aided Systems Theory - EUROCAST 2015. Lecture Notes in Computer Science, roč. 9520. Zurich: Springer International Publishing, 2015, s. 605-614. ISBN 978-3-319-27340-2. ISSN 0302-9743.
    Detail

  • 2014

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors. In: Proceedings of 15th International Workshop on Microprocessor Test and Verification (MTV 2014). Austin, TX: IEEE Computer Society, 2014, s. 83-89. ISBN 978-1-4673-6858-2.
    Detail

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors. Brno: Fakulta informačních technologií VUT v Brně, 2014.
    Detail

  • 2013

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. An Abstraction of Multi-Port Memories with Arbitrary Addressable Units. In: Proceedings of the 14th Computer Aided Systems Theory. Las Palmas de Grand Canaria: Universidad de Las Palmas de Gran Canaria, 2013, s. 254-255. ISBN 978-84-695-6971-9.
    Detail

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. An Abstraction of Multi-Port Memories with Arbitrary Addressable Units. In: Computer Aided Systems Theory - EUROCAST 2013. Lecture Notes in Computer Science, roč. 8111. Berlin Heidelberg: Springer Verlag, 2013, s. 460-468. ISBN 978-3-642-53855-1.
    Detail

  • 2012

    CHARVÁT Lukáš, SMRČKA Aleš a VOJNAR Tomáš. Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description. In: Proceedings of the 13th International Workshop on Microprocessor Test and Verification (MTV 2012). Austin, TX: Institute of Electrical and Electronics Engineers, 2012, s. 6-12. ISBN 978-1-4673-4441-8.
    Detail

  • 2010

    SMRČKA Aleš a VOJNAR Tomáš. Verification of Asynchronous and Parametrized Hardware Designs. FIT Monograph. Brno: Fakulta informačních technologií VUT v Brně, 2010. ISBN 978-80-214-4214-6.
    Detail

    SMRČKA Aleš. Verification of Asynchronous and Parametrized Hardware Designs. Information Sciences and Technologies Bulletin of the ACM Slovakia, roč. 2, č. 2, s. 60-69. ISSN 1338-1237.
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  • 2008

    SMRČKA Aleš a VOJNAR Tomáš. Verifying Parametrised Hardware Designs Via Counter Automata. In: Hardware and Software, Verification and Testing. Lecture Notes in Computer Science, roč. 4899. Heidelberg: Springer Verlag, 2008, s. 51-68. ISSN 0302-9743.
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  • 2007

    SMRČKA Aleš, ŘEHÁK Vojtěch, VOJNAR Tomáš, ŠAFRÁNEK David, MATOUŠEK Petr a ŘEHÁK Zdeněk. Verifying VHDL Design with Multiple Clocks in SMV. In: Formal Methods: Applications and Technology. Lecture Notes in Computer Science, roč. 4346. Bonn: Springer Verlag, 2007, s. 148-164. ISSN 0302-9743.
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  • 2006

    HLÁVKA Petr, ŘEHÁK Vojtěch, SMRČKA Aleš, ŠAFRÁNEK David, ŠIMEČEK Pavel a VOJNAR Tomáš. Formal Verification of the CRC Algorithm Properties. In: MEMICS 2006 Second Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov, 2006, s. 55-62. ISBN 80-214-3287-X.
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    SMRČKA Aleš. High-level Modeling, Analysis and Verification of Programmable Hardware Design. Proceedings of the Junior Scientist Conference 2006. Vienna: Technische Universität Wien, 2006. ISBN 3-902463-05-8.
    Detail

    SMRČKA Aleš, ŘEHÁK Vojtěch, VOJNAR Tomáš, ŠAFRÁNEK David, MATOUŠEK Petr a ŘEHÁK Zdeněk. Verifying VHDL Design with Multiple Clocks in SMV. In: Proceedings of FMICS 2006. Bonn, 2006, s. 140-155.
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  • 2005

    SMRČKA Aleš. Abstract Model Verification of the Lookup Processor. In: Proceedings of MOSIS'05. Ostrava: MARQ, 2005, s. 138-145. ISBN 80-86840-10-7.
    Detail

    MATOUŠEK Petr, SMRČKA Aleš a VOJNAR Tomáš. High-level Modelling, Analysis, and Verification on FPGA-based Hardware Design. Brno: CESNET, zájmové sdružení právnických osob, 2005.
    Detail

    MATOUŠEK Petr, SMRČKA Aleš a VOJNAR Tomáš. High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. In: Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science 3725/2005, roč. 2005. Berlin: Springer Verlag, 2005, s. 371-375. ISBN 978-3-540-29105-3. ISSN 0302-9743.
    Detail

    SMRČKA Aleš. Towards Hardware Verification. In: Proceedings of the 11th Conference Student EEICT 2005. Volume 3. Brno: Fakulta informačních technologií VUT v Brně, 2005, s. 668-672. ISBN 978-80-214-2890-4.
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  • 2003

    SMRČKA Aleš. Universal disassembler. In: Proceedings of the International Conference and Competition - Student EEICT 2003. Brno: Fakulta elektrotechniky a komunikačních technologií VUT v Brně, 2003, s. 346-348. ISBN 80-214-2401-X.
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