Detail výsledku

A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation

LOJDA, J.; KOTÁSEK, Z. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 79-80. ISBN: 978-80-01-06178-7.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Lojda Jakub, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

In this presentation, an approach to fault-tolerant systems design and synthesis based onHigh-level Synthesis (HLS) is shown. A description and evaluation of the impacts of HLS optimizationmethods are shown as well. The higher reliability is achieved through modificationof input description in the C++ programming language, which the HLS synthesistools are based on. Our work targets SRAM-based FPGAs, which are prone toSingle Event Upsets (SEUs). For the evaluation of the impacts of faults we use our evaluation platform, which allows us to test fault toleranceproperties of the Design Under Test (DUT). The evaluation platform is based onfunctional verification combined with fault injection.

Klíčová slova

High-level Synthesis, Data-Path, CatapultC, Fault Tolerance, Fault-Tolerant, Robot Controller, C++

Rok
2017
Strany
79–80
Sborník
Proceedings of the 5th Prague Embedded Systems Workshop
Konference
The 5th Prague Embedded Systems Workshop
ISBN
978-80-01-06178-7
Vydavatel
Faculty of Information Technology, Czech Technical University
Místo
Roztoky u Prahy
BibTeX 
@inproceedings{BUT144442,
  author="Jakub {Lojda} and Zdeněk {Kotásek}",
  title="A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation",
  booktitle="Proceedings of the 5th Prague Embedded Systems Workshop",
  year="2017",
  pages="79--80",
  publisher="Faculty of Information Technology, Czech Technical University",
  address="Roztoky u Prahy",
  isbn="978-80-01-06178-7",
  url="https://www.fit.vut.cz/research/publication/11451/"
}
Soubory
Projekty
Algoritmy, metody návrhu a platforma pro many-core zpracování obrazu a videa s velkou propustností a malou spotřebou energie, MŠMT, Společné technologické iniciativy, 7H14002, zahájení: 2014-04-01, ukončení: 2017-06-30, ukončen
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, zahájení: 2016-01-01, ukončení: 2020-12-31, ukončen
Pokročilé paralelní a vestavěné počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-17-3994, zahájení: 2017-03-01, ukončení: 2020-02-29, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru