Logická simulace na transputerech

logic simulation, simulation accelerator, transputer

Simulators of digital circuits belong to important verification tools. Growing complexity of integrated circuits call for higher performance all design tools including simulators. Special hardware accelerators represent one of possible solutions. The paper deals with an experimental simulation system for logic simulation, the key component of which (the simulator) is implemented on a PC board with transputer modules. The objective of the work was to develop a simple transputer-based event-driven simulator so that some experiments can be done with it especially from the speeding up the simulation point of view. The whole simulation system consists of five main components: 1. Integrated user environment under MS Windows, from which all other programmes are invoked. 2. Modelled circuit description entry. The EDIF format of netlist was chosen as an input format. It can be generated by means of the OrCAD/SDT schematic editor and the NETLIST programme. 3. The stimulus and trace signals editor. 4. The simulator. Two types of simulators were implemented: a sequential one - running on a PC processor and a parallel one - running on transputers. 5. The simulation results viewer. Both simulators are table-driven. There are 13 built-in models, which include simple gates, flip-flops, counters and a decoder. Following tasks were solved during the parallel simulator development: - Algorithm parallelization. Very simple solution was chosen - all steps of the event-driven simulation algorithm are performed in a main process except for elements evaluation which is done parallel if several elements is to be evaluated. - Process network topology. Star and ring topologies were used. - Programming language. The ANSI C tool set was used. Several experiments were done with very simple circuits but with a necessity of several evaluation in a given simulation time. Both star and ring topologies were mapped to various physical configurations. The duration of simulation was measured both for the parallel and the sequential.simulator. The most important conclusion was that mainly because of very simple elements behaviour models used the sequential simulation was faster than the parallel one. But it is not generally valid in a case of elements with more complicated behaviour.