Detail publikace

Modeling and Prototyping of Signal and Image Processing Algorithms in VHDL

SLLAME Azeddien M.. Modeling and Prototyping of Signal and Image Processing Algorithms in VHDL. In: 10th International Conference on System Modelling Control SMC'01. 10th International Conference on System Modelling Control SMC'01. Lodz, 2001, s. 201-205. ISBN 83-7283-026-6.
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Sllame Azeddien M., Ing. (UPSY FIT VUT)
Rok
2001
Strany
201-205
Sborník
10th International Conference on System Modelling Control SMC'01
Řada
10th International Conference on System Modelling Control SMC'01
Konference
10th International Conference on System-Modelling-Control, Zakopane, PL
ISBN
83-7283-026-6
Místo
Lodz, PL
BibTeX 
@INPROCEEDINGS{FITPUB7138,
   author = "M. Azeddien Sllame",
   title = "Modeling and Prototyping of Signal and Image Processing Algorithms in VHDL",
   pages = "201--205",
   booktitle = "10th International Conference on System Modelling Control SMC'01",
   series = "10th International Conference on System Modelling Control SMC'01",
   year = 2001,
   location = "Lodz, PL",
   ISBN = "83-7283-026-6",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7138"
}
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