Detail výsledku

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L.; STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 51-58. ISBN: 0-7695-2399-4.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Pečenka Tomáš, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Strnadel Josef, Ing., Ph.D., UPSY (FIT)
Abstrakt

The paper describes the utilization of evolutionary algorithms for automatic discovery of benchmark circuits. The main objective of the paper is to show that relatively large and complex (benchmark) circuits can be evolved in case that only a given property (e.g. testability) is required and the function of the circuit is not considered. This principle is demonstrated on automatic discovery of benchmark circuits with predefined structural and diagnostic properties. Fitness evaluation for the proposed algorithm is based on testability analysis with linear time complexity. During the evolution, the solutions which are refused to be synthesized by a design system are excluded from the process of developing a new generation of benchmark circuits. The evolved circuits contain thousands of components and satisfy the required testability properties.

Klíčová slova

evolutionary design, digital circuit, testability analysis, VHDL

URL
Rok
2005
Strany
51–58
Sborník
Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware
Konference
The 2005 NASA/DoD Conference on Evolvable Hardware
ISBN
0-7695-2399-4
Vydavatel
IEEE Computer Society Press
Místo
Los Alamitos
BibTeX 
@inproceedings{BUT21515,
  author="Tomáš {Pečenka} and Zdeněk {Kotásek} and Lukáš {Sekanina} and Josef {Strnadel}",
  title="Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties",
  booktitle="Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware",
  year="2005",
  pages="51--58",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos",
  isbn="0-7695-2399-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/eh05/eh05bench.pdf"
}
Projekty
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru