Detail výsledku
DSP and FPGA Based Raster Image Processing Architecture
Granát Jiří, Ing., UPGM (FIT)
Herout Adam, prof. Ing., Ph.D., UPGM (FIT)
Zemčík Pavel, prof. Dr. Ing., dr. h. c., UPGM (FIT)
An embedded raster image processing architecture based on programmable logical chip (FPGA) connected to a digital signal processor (DSP) is proposed in the contribution. The FPGA device is used as an accelerator for the computationally critical parts of the raster image processing applications. The main advantage of the system is standalone operation, low power consumption and good performance/price and performance/power ratios.
Application development for systems containing programmable logic and processors is in many cases difficult. The contribution addresses this fact and proposes a novel application development system for the architecture. The contribution also explains the architecture from hardware and software points of view.
FPGA, DSP, configurable logical devices, image processing, raster graphics
@inproceedings{BUT22405,
author="Vítězslav {Beran} and Jiří {Granát} and Adam {Herout} and Pavel {Zemčík}",
title="DSP and FPGA Based Raster Image Processing Architecture",
booktitle="Proceedings of the Digital Technologies 2007 Workshop",
year="2006",
pages="1--6",
publisher="Zilina University Publisher",
address="Žilina"
}Prostředky pro rychlý vývoj HW-akcelerovaných vestavěných aplikací zpracování obrazu a videa, AV ČR, Informační společnost (Národní program výzkumu), 1ET400750408, zahájení: 2004-07-01, ukončení: 2008-12-31, ukončen