Detail publikace

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA Lukáš. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007, s. 243-246. ISBN 1424411610.
Název česky
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY FIT VUT)
URL
Abstrakt

TBD

Rok
2007
Strany
243-246
Sborník
2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Konference
The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, PL
ISBN
1424411610
Vydavatel
IEEE Computer Society
Místo
Gliwice, PL
BibTeX 
@INPROCEEDINGS{FITPUB8310,
   author = "Luk\'{a}\v{s} Sekanina",
   title = "Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
   pages = "243--246",
   booktitle = "2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2007,
   location = "Gliwice, PL",
   publisher = "IEEE Computer Society",
   ISBN = "1424411610",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8310"
}
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