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Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design

GAJDA Zbyšek a SEKANINA Lukáš. Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design. In: 2007 Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2007, s. 245-252. ISBN 9781595936974.
Název česky
Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design
Typ
článek ve sborníku konference
Jazyk
angličtina
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URL
Abstrakt
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In addition to standard gates, we utilize unconventional gates (such as the NAND/NOR gate and NOR/NAND gate) that consist of a few transistors but exhibit non-trivial 3-input logic functions. Novel implementations of adders and majority circuits evolved using these gates contain fewer transistors than the smallest existing implementations of these circuits. Moreover, it was shown that the use of these gates significantly improves the success rate of the search process.
Rok
2007
Strany
245-252
Sborník
2007 Genetic and Evolutionary Computation Conference
Konference
Genetic and Evolutionary Computation Conference , London, GB
ISBN
9781595936974
Vydavatel
Association for Computing Machinery
Místo
New York, US
BibTeX
@INPROCEEDINGS{FITPUB8367,
   author = "Zby\v{s}ek Gajda and Luk\'{a}\v{s} Sekanina",
   title = "Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design",
   pages = "245--252",
   booktitle = "2007 Genetic and Evolutionary Computation Conference",
   year = 2007,
   location = "New York, US",
   publisher = "Association for Computing Machinery",
   ISBN = "9781595936974",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8367"
}
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