Detail výsledku

Hardware Architecture for Packet Classification with Prefix Coloring

PUŠ, V.; KAJAN, M.; KOŘENEK, J. Hardware Architecture for Packet Classification with Prefix Coloring. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 231-236. ISBN: 978-1-4244-9753-9.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Puš Viktor, Ing., Ph.D., UIFS (FIT), UPSY (FIT)
Kajan Michal, Ing., UIFS (FIT), UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

Packet classification is a widely used operation in network security
devices. As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in hardware can achieve multigigabit
speeds, but suffer with great memory overhead. We propose a new algorithm
and hardware architecture which reduces memory requirements of
decomposition based methods for packet classification. The algorithm uses
prefix coloring to reduce large amount of Cartesian product rules at the
cost of an additional pipelined processing and a few bits added into
results of the longest prefix match operation. The proposed hardware
architecture is designed as a processing pipeline with the throughput of
266 million packets per second using commodity FPGA and one external
memory. The greatest strength of the algorithm is the constant time
complexity of the search operation, which makes the solution resistant to
various classes of network security attacks.

Klíčová slova

FPGA, SRAM, hardware, parallelism, classification

Rok
2011
Strany
231–236
Sborník
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011
ISBN
978-1-4244-9753-9
Vydavatel
IEEE Computer Society
Místo
Cottbus
BibTeX
@inproceedings{BUT76313,
  author="Viktor {Puš} and Michal {Kajan} and Jan {Kořenek}",
  title="Hardware Architecture for Packet Classification with Prefix Coloring",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="231--236",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9",
  url="https://www.fit.vut.cz/research/publication/9564/"
}
Soubory
Projekty
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
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Pracoviště
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