Detail výsledku

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

STRNADEL, J. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013. p. 24-29. ISBN: 978-1-4673-6133-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Strnadel Josef, Ing., Ph.D., UPSY (FIT)
Abstrakt

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

Klíčová slova

task, operating system, load monitoring, interrupt control, scheduling, overload prevention, priority space

URL
Rok
2013
Strany
24–29
Sborník
Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013
ISBN
978-1-4673-6133-0
Vydavatel
IEEE Computer Society
Místo
Brno
DOI
10.1109/DDECS.2013.6549783
BibTeX 
@inproceedings{BUT103418,
  author="Josef {Strnadel}",
  title="On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems",
  booktitle="Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2013",
  pages="24--29",
  publisher="IEEE Computer Society",
  address="Brno",
  doi="10.1109/DDECS.2013.6549783",
  isbn="978-1-4673-6133-0",
  url="https://www.fit.vut.cz/research/publication/10235/"
}
Soubory
Projekty
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, zahájení: 2011-01-01, ukončení: 2015-12-31, ukončen
Národní dofinancování projektu Reduced Certification Costs Using Trusted Multi-core Platforms, MŠMT, Společné technologické iniciativy, 7H10013, zahájení: 2010-04-01, ukončení: 2013-03-31, řešení
Pokročilé bezpečné, spolehlivé a adaptivní IT, VUT, Vnitřní projekty VUT, FIT-S-11-1, zahájení: 2011-01-01, ukončení: 2013-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru