Detail výsledku

Hardware Architecture for the Fast Pattern Matching

KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Hardware Architecture for the Fast Pattern Matching. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013. p. 120-123. ISBN: 978-1-4673-6133-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kaštil Jan, Ing., Ph.D., UPSY (FIT)
Košař Vlastimil, Ing., Ph.D., UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

As the speed of current computer networks in-
creases, it is necessary to protect networks by security systems
such as firewalls and Intrusion Detection Systems (IDS) operating
at multigigabit speeds. As attacks on modern networks became
more and more complex, it is necessity to detect attack placed
not only in single packet but at the level of network flows. Pattern
matching in the network flows is the time-critical operation
of many modern IDS. Most of the regularly used patterns
are described by the regular expression. This work describes
advanced hardware architecture for the fast regular expression
matching based on the perfect hashing. The proposed architecture
is scalable and can achieve multigigabit throughput per network
flow.

Klíčová slova

pattern matching, intrussion detection system, regular expression, FPGA

Rok
2013
Strany
120–123
Sborník
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013
ISBN
978-1-4673-6133-0
Vydavatel
IEEE Computer Society
Místo
Brno
BibTeX 
@inproceedings{BUT103447,
  author="Jan {Kaštil} and Vlastimil {Košař} and Jan {Kořenek}",
  title="Hardware Architecture for the Fast Pattern Matching",
  booktitle="2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  year="2013",
  pages="120--123",
  publisher="IEEE Computer Society",
  address="Brno",
  isbn="978-1-4673-6133-0"
}
Projekty
Pokročilé bezpečné, spolehlivé a adaptivní IT, VUT, Vnitřní projekty VUT, FIT-S-11-1, zahájení: 2011-01-01, ukončení: 2013-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru