Detail výsledku
A Multi-protocol cache controller
Dvořák Václav, prof. Ing., DrSc.
Bus-based shared memory multiprocessors with per-processor caches useeither invalidation or update protocols to maintain cache coherence.This paper suggests mixing protocols for different data objects withina single application, depending on whatever protocol is more efficientfor an access pattern to a given object. The model of a two-protocolcache coherence controller has been created in CSP-based Transimlanguage. Each cache line is tagged not only with the state, but alsowith the protocol type. Two most frequent 4-state, write-back protocolsare implemented: MESI (invalidation) and Dragon (update) protocol. Themodel will be used for experimental evaluation of the proposedcontroller, which could then be used for processor cores with primarycaches in SoC or for secondary caches in multiprocessors with standardmicroprocessors.
Cache coherence protocols, Bus multiprocessor systems, Tuning characteristics.
@inproceedings{BUT13782,
author="Vladimír {Kutálek} and Václav {Dvořák}",
title="A Multi-protocol cache controller",
booktitle="IFAC Workshop on Programmable devices and systems - PDS 2003",
year="2003",
pages="220--225",
publisher="VŠB - Technical University of Ostrava",
address="Ostrava",
isbn="0-08-044130-0"
}