Detail výsledku

Instruction-level Programming Approach for Very Long Instruction Word Digital Signal Processors

FRÝZA, T.; MEGO, R. Instruction-level Programming Approach for Very Long Instruction Word Digital Signal Processors. In Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017). Batumi, Georgia: 2018. p. 518-521. ISBN: 978-1-5386-1911-7.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Frýza Tomáš, doc. Ing., Ph.D., UREL (FEKT)
Mego Roman, Ing., Ph.D., UREL (FEKT)
Abstrakt

This paper is focused on the benefit of low-level programming of Gigital Signal Processors (DSP) with Very Long Instruction Word (VLIW) architecture. Scecifically, the process of hardware resources allocation which is outlined in text and proved by basic matrix benchmarks. Compare to available library functions, the proposed results decrease the number of execution cycles by tens of percent for smaller matrix dimensions and help developers to solve critical parts of their applications in the instruction-level approach.

Klíčová slova

DSP, VLIW, instruction-level, low-level, matrix, assembly, C6678

URL
Rok
2018
Strany
518–521
Sborník
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017)
Konference
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
ISBN
978-1-5386-1911-7
Místo
Batumi, Georgia
DOI
10.1109/ICECS.2017.8292060
UT WoS
000426974200125
EID Scopus
2-s2.0-85047487125
BibTeX 
@inproceedings{BUT141212,
  author="Tomáš {Frýza} and Roman {Mego}",
  title="Instruction-level Programming Approach for Very Long Instruction Word Digital Signal Processors",
  booktitle="Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017)",
  year="2018",
  pages="518--521",
  address="Batumi, Georgia",
  doi="10.1109/ICECS.2017.8292060",
  isbn="978-1-5386-1911-7",
  url="https://ieeexplore.ieee.org/document/8292060/"
}
Pracoviště
Ústav radioelektroniky (UREL)
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