Detail výsledku

A Methodology for Designing Communication Architectures for Multiprocessor SoCs

DVOŘÁK, V.; KUTÁLEK, V. A Methodology for Designing Communication Architectures for Multiprocessor SoCs. Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society, 2003. p. 455-458. ISBN: 0-7695-2003-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Dvořák Václav, prof. Ing., DrSc.
Kutálek Vladimír, Ing., Ph.D., FIT (FIT)
Abstrakt

Multiprocessor SoCs (MSoCs) for network and stream processing have to cope with growing speed and flexibility requirements of new complex packet processing tasks. Performance optimization of a homogenous network of CPUs in a certain application leads basically to optimization of CPUs interconnect and communication algorithms. Several on-chip communication architectures are compared with respect to their cost, simplicity of routing algorithms, and performance in collective communications. It is shown, that if group communication patterns are considered in certain proportions, the fat cube architecture rather than Octagonal architecture may have the best performance/cost figure. A methodology for designing efficient on-chip interconnects on regular group communication patterns is suggested. It may be useful if the system is targeted for specific class of applications.

Klíčová slova

Communication architecture, Multiprocessor SoC, Stream multiprocessing, Group communication complexity

Rok
2003
Strany
455–458
Sborník
Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003
Konference
EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools
ISBN
0-7695-2003-0
Vydavatel
IEEE Computer Society
Místo
Belek
BibTeX
@inproceedings{BUT14162,
  author="Václav {Dvořák} and Vladimír {Kutálek}",
  title="A Methodology for Designing Communication Architectures for Multiprocessor SoCs",
  booktitle="Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003",
  year="2003",
  pages="455--458",
  publisher="IEEE Computer Society",
  address="Belek",
  isbn="0-7695-2003-0"
}
Projekty
Predikce a ladění paralelní výkonnosti, GAČR, Standardní projekty, GA102/02/0503, zahájení: 2002-01-01, ukončení: 2004-12-31, ukončen
Pracoviště
Nahoru