Detail výsledku

A Processor Optimization Framework for a Selected Application

PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. A Processor Optimization Framework for a Selected Application. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 564-574. ISBN: 978-1-5386-5710-2.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Podivínský Jakub, Ing., Ph.D., UPSY (FIT)
Čekan Ondřej, Ing., Ph.D., UPSY (FIT)
Krčma Martin, Ing., Ph.D., UPSY (FIT)
Burget Radek, doc. Ing., Ph.D., UIFS (FIT)
Hruška Tomáš, prof. Ing., CSc., UIFS (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

A processor plays the main role in almost every electronics system. The use of a general purpose processor may not be profitable for a specific application, because the processor is designed for a wide set of applications. Application Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where one application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking its possible configurations of key parameters (number of registers, size of caches, instruction set modification, etc.). The paper also presents designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modification, the Codasip Studio tool is used. It allows to generate all tools needed for compilation, simulation, and hardware mapping which are needed in process of ASIP design. The experiments are carried on RISC-V (Reduced Instruction Set Computing) processor described in Codasip Studio.

Klíčová slova

Processor optimization, ASIP, Codasip Studio, embedded system, RISC-V

Rok
2018
Strany
564–574
Sborník
Proceedings of IEEE East-West Design & Test Symposium
Konference
16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM
ISBN
978-1-5386-5710-2
Vydavatel
IEEE Computer Society
Místo
Kazan
DOI
UT WoS
000517795800076
EID Scopus
BibTeX
@inproceedings{BUT155019,
  author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="A Processor Optimization Framework for a Selected Application",
  booktitle="Proceedings of IEEE East-West Design & Test Symposium",
  year="2018",
  pages="564--574",
  publisher="IEEE Computer Society",
  address="Kazan",
  doi="10.1109/EWDTS.2018.8524733",
  isbn="978-1-5386-5710-2",
  url="https://www.fit.vut.cz/research/publication/11689/"
}
Soubory
Projekty
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, zahájení: 2016-01-01, ukončení: 2020-12-31, ukončen
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