Detail výsledku

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller

PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; KOTÁSEK, Z. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 229-236. ISBN: 978-1-5386-7376-8.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Podivínský Jakub, Ing., Ph.D., UPSY (FIT)
Lojda Jakub, Ing., Ph.D., UPSY (FIT)
Čekan Ondřej, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

Various electronic systems play an important role in our everyday lives. Some of them serve for fun or to make our lives easier. These systems are useful but not necessary; when they malfunction, the consequences are not critical. On the other hand, there are systems which are more or less critical, and their failure can cause undesirable consequences. For example, a failure in medicine, aviation, the army or automotive systems can cause high economic losses and/or endanger human health. These systems must be protected against the impact of faults, and flawless operation must be ensured. Fault tolerance is one of the techniques that will ensure this. There are many fault-tolerance methodologies targeted towards various systems and technologies, and new methodologies are being investigated. It is also important to verify these techniques; this is the main topic of this paper. An evaluation platform for testing fault-tolerance methodologies targeted towards SRAM-based FPGAs (Field Programmable Gate Arrays) is presented and demonstrated. A robot for seeking a path through a maze and the processor-based robot controller serve as an experimental system case study. Experimental results with the unhardened and hardened versions of the processor-based robot controller are presented and discussed.

Klíčová slova

Soft-core Processor, NEO430, TMR, FPGA, Fault
Tolerance, Robot Controller, Reconfiguration.

Rok
2018
Strany
229–236
Sborník
Proceedings of the 2018 21st Euromicro Conference on Digital System Design
Konference
21st Euromicro Conference on Digital Systems Design
ISBN
978-1-5386-7376-8
Vydavatel
IEEE Computer Society
Místo
Praha
DOI
UT WoS
000537466600035
EID Scopus
BibTeX
@inproceedings{BUT155030,
  author="Jakub {Podivínský} and Jakub {Lojda} and Ondřej {Čekan} and Zdeněk {Kotásek}",
  title="Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller",
  booktitle="Proceedings of the 2018 21st Euromicro Conference on Digital System Design",
  year="2018",
  pages="229--236",
  publisher="IEEE Computer Society",
  address="Praha",
  doi="10.1109/DSD.2018.00051",
  isbn="978-1-5386-7376-8",
  url="https://www.fit.vut.cz/research/publication/11705/"
}
Soubory
Projekty
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, zahájení: 2016-01-01, ukončení: 2020-12-31, ukončen
Pokročilé paralelní a vestavěné počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-17-3994, zahájení: 2017-03-01, ukončení: 2020-02-29, ukončen
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